PCI Express 3.0 Base specification announced

November 23, 2010

Picture of PCI boardPCI Express 3.0 Base specification revision 3.0 has finally seen the light. The specification, that had been delayed on several occasions, includes a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies.

PCIe 3.0 is the next evolution of the ubiquitous and general-purpose PCI Express I/O standard. At 8GT/s bit rate, the interconnect performance bandwidth is doubled over PCIe 2.0, while preserving compatibility with software and mechanical interfaces, representing the most optimum tradeoff between manufacturability, cost, power and compatibility.In contrast, the original PCIe specification supported a 2.5GT/s bit rate and PCIe 2.0 supported 5GT/s.

Additionally, PCI-Express 3.0 implements the encryption scheme 128b/130b, providing almost one hundred percent efficiency, and also includes improvements in areas such as mechanisms for dynamically adjusting power consumption, the notification of admission for latency, scalability, architecture and so on.

The key requirement for evolving the PCIe architecture is to continue to provide performance scaling consistent with bandwidth demand from leading applications with low cost, low power and minimal perturbations at the platform level. One of the main factors in the wide adoption of the PCIe architecture is its sensitivity to high-volume manufacturing materials and tolerances such as FR4 boards, low-cost clock sources, connectors and so on. In providing full compatibility, the same topologies and channel reach as in PCIe 2.0 are supported for both client and server configurations. Another important requirement is the manufacturability of products using the most widely available silicon process technology. For the PCIe 3.0 architecture, the PCI-SIG believes a 65nm process or better will be required to optimize on silicon area and power.

PCI Express connectors

PCI Express has replaced AGP as the default interface for graphics cards on new systems. With a few exceptions, all graphics cards being released as of 2009 and 2010 from ATI and NVIDIA use PCI Express. NVIDIA uses the high bandwidth data transfer of PCIe for its Scalable Link Interface (SLI) technology, which allows multiple graphics cards of the same chipset and model number to be run in tandem, allowing increased performance. ATI also has developed a multi-GPU system based on PCIe called CrossFire. AMD and NVIDIA have released motherboard chipsets which support up to four PCIe ×16 slots, allowing tri-GPU and quad-GPU card configurations.

The new specification is currently available only to members of the PCI-SIG, the association of members of the microcomputer industry set up for the purpose of monitoring and enhancing the development of the Peripheral Component Interconnect (PCI) architecture, among which are companies like AMD, Dell, HP, IBM, Intel, LSI, NVIDIA, or Oracle. The first products to support PCIe 3.0 interface are expected to hit the market some time after the second quarter of 2011. The initial target applications for PCIe 3.0 are expected to be graphics. Ethernet, Infinband, storage and PCIe switches will continue to drive the bandwidth evolution for the PCIe architecture and these applications are the current targets of the PCIe 3.0 technology.